1. Field of the Invention
The present invention relates to a delay adjustment circuit for a delay locked loop. More particularly, the invention relates to a delay adjustment circuit for a delay locked loop, which is mainly loaded between semiconductor integrated circuits of clock synchronous types or the like, applied to a delay locked loop for synchronizing an internal clock signal used at an internal circuit based on an external control signal with an external clock signal, and provided with functions of adjusting a delay quantity of a rough interval, and adjusting a delay quantity of a fine interval.
2. Description of the Prior Art
It is a known fact that information electronic devices such as a portable telephone set have widely been used in recent years. It is also well known that many of the information electronic devices generate internal clock signals to be used at their internal circuits based on external control signals.
It is generally known that a delay locked loop (abbreviated to DLL, hereinafter) is used in order to synchronize the internal clock signals used at the internal circuits with external clock signals based on the above external control signals.
A DLL delay adjustment circuit has conventionally been provided, which is applied to the DLL for synchronizing the internal clock signals used at the internal circuits with the external clock signals based on the external control signals, and provided with functions of adjusting a delay quantity of a rough interval, and a delay quantity of a fine interval. It is well known that in this DLL delay adjustment circuit, with a higher speed and lower power consumption requested of the semiconductor integrated circuit in recent years, allowable ranges of various standards such as an output delay error (jitter) have tended to become very narrow.
FIG. 1 is a circuit block diagram schematically showing a basic configuration of a conventional DLL delay adjustment circuit.
The conventional DLL delay adjustment circuit 100 is configured by serially connecting a plurality (three in this case) of first delay elements D1 to D3 having maximum delay values of delay quantity adjustment of a fine interval to a selection circuit (selector) S. This conventional DLL delay adjustment circuit 100 is configured in such a manner that a second delay element FA for adjusting a delay quantity of a fine interval is connected to an output side of the selection circuit S, input clock signals CLK-IN are entered to the delay elements D1 to D3, and the selection circuit S, and accordingly delay outputs obtained from the delay elements D1 to D3 are respectively entered to the selection circuit S.
Also, the conventional DLL delay adjustment circuit 100 is configured in such a manner that delay outputs obtained from the delay elements D1 to D3 are set as a delay quantity of a rough interval, first delay. control signals A1 and A2 for selection control are entered to the selection circuit S from an external unit, and second delay control signals B1, B2, B3 and B4 for setting a delay quantity of a fine interval are entered to the second delay element FA from the external unit.
In the conventional DLL delay adjustment circuit 100, the delay quantity of a fine interval set by the second delay element FA based on the second delay control signals B1, B2, B3 and B4 is added to the delay quantity of a rough interval obtained as an output of roughly adjusted delays from the delay elements D1 to D3 selected by the selection circuit S based on the first delay control signals A1 and A2, and a result of the addition can be obtained as an output clock signal CLK-OUT.
Incidentally, in the DLL delay adjustment circuit 100, the input clock signals CLK-IN and the first delay control signals A1 and A2 entered to the selection circuit S can be considered as a delay quantity rough adjustment input signal system L1 for adjusting a delay quantity of a rough interval, and the second delay control signals B1, B2, B3 and B4 as a delay quantity fine adjustment input signal system L2 for adjusting a delay quantity of a fine interval.
FIG. 2 is a timing chart showing a relation of output waveforms among delay quantity adjustment of a rough interval, delay quantity adjustment of a fine interval, and a last clock total delay quantity by delay quantity adjusting operations thereof in the DLL delay adjustment circuit. It is specifically shown that when delay quantity adjustment of a fine interval is made by 0.2 ns, 1ns being a maximum, delay quantity adjustment of a rough interval is carried out as carrying of the delay quantity adjustment of a fine interval, and an output clock signal CLK-OUT is obtained by a last clock total delay quantity resulted from addition of those delay quantities.
Other conventional technologies have been presented regarding DLL delay adjustment. For example, Japanese Patent A No. 2001-56723 discloses xe2x80x9cSEMICONDUCTOR INTEGRATED CIRCUITxe2x80x9d. A known technology regarding delay adjustment of a phase locked loop (called PLL) is disclosed as, for example xe2x80x9cCONTINUOUSLY ADJUSTABLE DELAY LOCKED LOOPxe2x80x9d in Japanese Patent A No. 11 (1999)-168376. Japanese Patent A No. 2000-323969 discloses xe2x80x9cDIGITAL PLL APPARATUS AND DELAYLER THEREOFxe2x80x9d. Moreover, a known technology regarding delay quantity adjustment for general high-speed digital circuit is disclosed as xe2x80x9cDELAY ADJUSTMENT CIRCUITxe2x80x9d in Japanese Patent A No. 3 (1991)-35613.
However, in the case of the DLL delay adjustment circuit shown in FIG. 1, for example, in FIG. 3, if a relation between changing points of signals (obtained at input terminal names D1 and D2 on the selection circuit S) obtained by passing of the input clock signal CLK-IN as data at the selection circuit S through the delay elements D1 and D2, and delay control signals A2 (xe2x80x9c01xe2x80x9d section):A1 (xe2x80x9c10xe2x80x9d section) as selection signals indicating switching operations for those signals is set in operation by a shown timing, then noise is generated in an output signal (obtained from an output terminal name Y on the section circuit S).
If the delay quantity adjustment described above with reference to FIG. 2 is not operated normally, an output delay error similar to that shown in FIG. 4 occurs in a last clock total delay quantity at the output clock signal CLK-OUT. That is, in FIG. 4, if delay quantity adjustment of a rough interval is not operated normally, when a timing of a waveform of delay quantity adjustment of a fine interval related to the delay quantity fine adjustment input signal system L2 is shifted to be delayed from a waveform of a delay quantity adjustment of a rough interval related to the delay quantity rough adjustment input signal system L1 (when timings of selection of the delay quantity adjustment of a fine interval and selection of the delay quantity adjustment of a rough interval are not identical to each other), the output clock signal CLK-OUT is obtained while output delay errors of 1 ns and 2 ns occur in the last clock total delay quantity.
In order to deal with the noise generated in the output of the selection circuit S and the output delay error generated in the output clock signal CLK-OUT of the delay element FA, all the delay control signals A1, A2, and B1 to B4 can be controlled by retiming with the output clock signal CLK-OUT. In this case, however, time for retiming must be secured in a period from the output of the selection circuit S to obtaining of the output clock signal CLK-OUT of the delay element FA. Consequently, a significant adverse effect is placed on maintenance of a high-speed operation.
In short, in the case of the conventional DLL delay adjustment circuit, because of a functional configuration, it is difficult to achieve a high-speed operation after prevention of noise generation or output delay error generation during switching by delay control signals.
An object of the present invention is to eliminate the foregoing drawbacks of the conventional art, and its technical task is to provide a DLL delay adjustment circuit capable of achieving a high-speed operation after prevention of noise generation or output delay error generation during switching by delay control signals.
In accordance with the present invention, a delay adjustment circuit for a delay locked loop comprises: a delay rough adjustment circuit unit for carrying out delay quantity adjustment of a rough interval, the circuit unit including first delay elements having a maximum delay value of delay quantity adjustment of an interval finer than the rough interval, and divided into two systems of odd-number and even-number stages to carry out delay quantity adjustment of the rough interval with respect to an input clock signal, and selection circuits for receiving first delay control signals from an external unit to select and control delay outputs obtained from the first delay elements as delay quantities of the rough interval, and dividing the first delay elements into the two systems of the odd-number and even-number stages; and a delay fine adjustment circuit unit including second delay elements of two systems for receiving outputs of roughly adjusted delays of the odd-number and even-number stages of the two systems, selectively carrying out fine interval delay quantity adjustments of the two systems by opposite operations, and obtaining the output clock signal. In this case, the delay fine adjustment circuit unit adds a delay quantity of a fine interval set by the second delay elements to a delay quantity of a rough interval obtained as an output of the roughly adjusted delay from the first delay elements selected by the selection circuits based on the first delay control signal, and outputs a result of the addition as the output clock signal based on the second delay control signals. The first delay control signals are separately transmitted to the selection circuits of the odd-number and even-number stages to select delay outputs of the plurality of first delay elements, and control is executed to switch outputs of roughly adjusted delays of the two systems when delay differences of fine interval delay quantity adjustments between the two systems become equal to each other.
In accordance with the present invention, the delay adjustment circuit for a delay locked loop can employ various proper modes descried below.
That is, in the delay adjustment circuit for a delay locked loop according to the invention, the delay rough adjustment circuit unit includes a plurality of delay selection circuits provided with selection functions by the selection circuits of the odd-number and even-number stages, and fine interval delay quantity adjusting functions by the plurality of first delay elements. The delay selection circuits of the odd-number and even-number stages are configured by combining and connecting first delay selection circuits operated for output according to a HIGH level signal from an external unit based on the input clock signal, second delay selection circuits operated for output according to the first delay control signals based on the input clock signal, and third delay selection circuits operated for output according to a LOW level signal from the external unit.
The delay adjustment circuit for a delay locked loop according to the invention further comprises an output selection circuit for selectively outputting one of inputs of output clock signals outputted from the second delay elements of the two systems based on an enable signal from an external unit generated in synchronization with the second delay control signals.
In the delay adjustment circuit for a delay locked loop according to the invention, the second delay elements of the two systems selectively switch output operations based on an enable signal from an external unit generated in synchronization with the second delay control signals.
In the delay adjustment circuit for a delay locked loop according to the invention, for the enable signal, one of normal rotation is transmitted to one of the second delay elements of the two systems, and one of reverse rotation is transmitted to the other. For the second delay control signals, one of reverse rotation is transmitted to one of the second delay elements of the two systems, and one of normal rotation is transmitted to the other.
In the delay adjustment circuit for a delay locked loop according to the invention, the second delay elements of the two systems switch output operations based on gray codes transmitted as the second delay control signals.
In the delay adjustment circuit for a delay locked loop according to the invention, the second delay elements of the two systems switch output operations based on binary codes transmitted as the second delay control signals.